1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a cell contact pad.
2. Description of the Related Art
Following development of increase of storage capacity of a semiconductor memory device, a one gigabit DRAM (Hereinafter Dynamic Random Access Memory is referred to as DRAM for short) is in practical use. A dimension of an element used in the large capacity semiconductor memory device is miniaturized, and specifically, an interval between word lines (row lines) of the DRAM is reduced following miniaturization of a memory cell. As a result, formation of an interlayer film to be buried or embedded in the row lines is becoming difficult. Since capability of transistors has advanced, low temperature-heat treatment is required and the further lowering of the temperature is indispensable to form the interlayer films. In addition, forming an interlayer insulating film having excellent coatability at relatively low temperature becomes difficult and burying the space between the word lines becomes further difficult.
As a first conventional example, problems caused by the defective burying will be explained below referring to FIGS. 1A through 1D. As shown in FIG. 1A, a device separation region 52 is formed in a silicon substrate 51, and a gate electrode film having a gate insulating film 53, a gate lower electrode 54, a gate upper electrode 55, and a mask nitride film 56 is formed. Further, a patterning is performed so as to form a gate electrode. Furthermore, a side wall insulating film 57 for forming a cell contact hole is formed around the gate electrode. At this time, a gate electrode 7 of the memory cell and a gate electrode 13 of a peripheral circuit are simultaneously formed. Then, an interlayer insulating film 58 is formed. However, when an interval between the gates is narrow, a buried defect occurs so that a void 59 is formed. Next, as shown in FIG. 1B, a resist pattern of a contact hole is formed at a cell portion using a typical photolithography process. Further, a contact hole 60 in the cell is formed using the resist pattern as a mask, under a self-aligned etching condition having an etching selectivity against a nitride film.
Next, as shown in FIG. 1C, polysilicon is buried in the contact hole to thereby form a contact plug 61. In this event, when the void 59 is formed, the polysilicon also grows in the void 59. Further, although there is no problem in a direction perpendicular to the word line, as shown in FIG. 1C, polysilicon 62 intrudes in a void portion and thereby an electrical short circuit occurs between polysilicon plugs because the void 59 is formed between the contact plugs 61 in a parallel direction with the word line, as shown in FIG. 1D.
In order to solve these problems, the inventor of the present invention applied for patents as prior applications, i.e., Japanese Unexamined Patent Application Publication No. 11-340436 and Japanese Unexamined Patent Application Publication No. 2000-091530. In the Japanese Unexamined Patent Application Publication No. 11-340436 and the Japanese Unexamined Patent Application Publication No. 2000-091530, a cell contact pad process is described, in which a cell contact is formed not by means of contact hole, but by means of remainder pattern of an electric conductor as a structure of the cell contact. Hereinbelow, a cell contact pad method will be explained as a second conventional example (hereinafter, the cell contact pad is referred to as a cell-con pad).
In the cell-con pad method shown in FIGS. 2, 3A, and 3B, the device separation region 52 is formed in the silicon substrate 51 and the gate electrode film including the gate insulating film 53, the gate lower electrode 54, the gate upper electrode 55, and the mask nitride film 56 is formed. The patterning of the cell gate electrode 7 of the memory cell is performed and the side wall insulating film 57 for forming the cell contact hole is formed around the gate electrode. Thereafter, the polysilicon is deposited and the patterning of the polysilicon is carried out so that a cell-con pad 10 is formed. Thereafter, an interlayer insulating film 11 is formed and the patterning of the interlayer insulating film 11 and the mask nitride film 56 is performed. Further, the patterning of the gate electrode 13 at a peripheral portion is performed. Since the interlayer insulating film 11 is formed after the cell-con pad 10 is formed, even when a void 22 is formed in the interlayer insulating film 11 between the gate electrodes 7, the electrical short circuit does not occur between the cell-con pads 10.
However, even in these cell-con pad methods, below mentioned problems are found on the basis of knowledge of the inventor of the present invention. FIG. 3B is a cross-section along a cutting line Y-Y′ of FIG. 2, and when the interlayer insulating film 11 between the cell gate electrodes 7 is defectively buried, a void 31 is generated at a periphery along the cell gate electrode 7. Further, a cell-con pad 30 of an outermost periphery is exposed to wet liquid, gas, or the like, while the peripheral gate electrode 13 is formed and the interlayer insulating film on the peripheral gate is formed. Further, as shown in FIG. 2, the gas or the like may has to intrude or invade into the cell-con pad 10 to be located deeper back, through an approaching path 32 including space between the cell gate electrodes and between the cell-con pads. The intruded gas, moisture, or the like decays the electrodes and causes the portion, at which a diffusion layer and the cell-con pad 10 come in contact with each other, to have high resistivity.
Further, with regard to the miniaturization of the memory cell, another patent application, namely Japanese Unexamined Patent Application Publication No. 2001-118998 is found, for example. In the Japanese Unexamined Patent Application Publication No. 2001-118998, a technology is described in which a dummy contact pad is provided at an outer periphery of the memory cell so that an electrical short circuit between a bit line and a word line is thereby prevented. However, any one of the patent applications does not include recognition of the aforementioned problems that is found by the inventor of the present invention, and any of the means for solving the problems is not described as well.
As described above, in the conventional cell-con pad method that forms a memory cell, the cell-con pad 30 of an outermost periphery of the memory cell is exposed to the wet liquid, gas, or the like in a process, such as the patterning of the gate electrode of the peripheral circuit or the like. As a result, the gas or the like intrudes into the cell-con pad 10 to be located deeper back through an approaching path 32 including space between the cell gate electrodes and between the cell-con pads. The intruded gas, moisture, or the like decays the electrodes and causes a portion, at which a diffusion layer and the contact come in contact with each other, to have high resistivity. However, any one of the patent applications does not include recognition of the aforementioned problems and any one of the means for solving the problems is not described as well.